diff options
| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-04-02 18:11:32 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-04-02 18:11:32 +0000 |
| commit | bee8a094af3d93c2e8ef057d8bfec38c29904191 (patch) | |
| tree | e9651a2ffb6a97e73ca80649a6c24f054eab44fe /lib/Target/X86/InstSelectSimple.cpp | |
| parent | 79ee87b1bba3f35ed8a7bcc1e598304836a22124 (diff) | |
Clean up code a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12615 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/InstSelectSimple.cpp')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 79181ecaa4..fa7eef1713 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -1674,18 +1674,11 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB, if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) { if (CI->isNullValue()) { unsigned op1Reg = getReg(Op1, MBB, IP); - switch (Class) { - default: assert(0 && "Unknown class for this function!"); - case cByte: - BuildMI(*MBB, IP, X86::NEG8r, 1, DestReg).addReg(op1Reg); - return; - case cShort: - BuildMI(*MBB, IP, X86::NEG16r, 1, DestReg).addReg(op1Reg); - return; - case cInt: - BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg).addReg(op1Reg); - return; - } + static unsigned const NEGTab[] = { + X86::NEG8r, X86::NEG16r, X86::NEG32r + }; + BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg); + return; } } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0)) if (CFP->isExactlyValue(-0.0)) { @@ -1716,8 +1709,8 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB, // add X, 1 -> inc X if (OperatorClass == 0 && Op1C->equalsInt(1)) { - static unsigned const DECTab[] = { X86::INC8r, X86::INC16r, X86::INC32r }; - BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r); + static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r }; + BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r); return; } |