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| author | Chris Lattner <sabre@nondot.org> | 2006-11-04 05:27:39 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-11-04 05:27:39 +0000 |
| commit | af53a87052f41664ff5962731d0b64e3b51a5501 (patch) | |
| tree | 8122243d67a0ee81de302cc8713ddaf146271bfb /lib/Target/TargetMachineRegistry.cpp | |
| parent | efe9f4a3b69eb2a31f006476996c8ef722345193 (diff) | |
Go through all kinds of trouble to mark 'blr' as having a predicate operand
that takes a register and condition code. Print these pieces of BLR the
right way, even though it is currently set to 'always'.
Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/TargetMachineRegistry.cpp')
0 files changed, 0 insertions, 0 deletions