diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:44:00 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 13:44:00 +0000 |
| commit | 3360da97724aee08ea8d0af11d8589da33bcbba4 (patch) | |
| tree | e377d15f578bbb9327385714983a57eab6613ab2 /lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp | |
| parent | 4cad7d29fc65c22ff5b4147000368e88ec77c5b9 (diff) | |
Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp')
| -rw-r--r-- | lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp index 568c99b0b3..867876410f 100644 --- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp @@ -52,6 +52,8 @@ namespace { const char* Modifier = 0); void printRIAddrOperand(const MachineInstr *MI, int OpNum, const char* Modifier = 0); + void printRRIAddrOperand(const MachineInstr *MI, int OpNum, + const char* Modifier = 0); bool printInstruction(const MachineInstr *MI); // autogenerated. void printMachineInstruction(const MachineInstr * MI); @@ -196,10 +198,31 @@ void SystemZAsmPrinter::printRIAddrOperand(const MachineInstr *MI, int OpNum, printOperand(MI, OpNum+1); // Print base operand (if any) - if (!(Base.isReg() && Base.getReg() == SystemZ::R0D)) { + if (Base.getReg()) { O << '('; printOperand(MI, OpNum); O << ')'; } } +void SystemZAsmPrinter::printRRIAddrOperand(const MachineInstr *MI, int OpNum, + const char* Modifier) { + const MachineOperand &Base = MI->getOperand(OpNum); + const MachineOperand &Index = MI->getOperand(OpNum); + + // Print displacement operand. + printOperand(MI, OpNum+2); + + // Print base operand (if any) + if (Base.getReg()) { + O << '('; + printOperand(MI, OpNum); + if (Index.getReg()) { + O << ','; + printOperand(MI, OpNum+1); + } + O << ')'; + } else + assert(!Index.getReg() && "Should allocate base register first!"); +} + |
