Make the addressing modes smarter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24795 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 21 insertions, 10 deletions

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a17637a46a..0e9210dcfe 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -235,18 +235,33 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
   ScheduleAndEmitDAG(DAG);
 }
 
-bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand N, SDOperand &R1, 
+bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 
                                        SDOperand &R2) {
-  // FIXME: This should obviously be smarter.
-  R1 = Select(N);
+  if (Addr.getOpcode() == ISD::ADD) {
+    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
+        Predicate_simm13(Addr.getOperand(1).Val))
+      return false;  // Let the reg+imm pattern catch this!
+    R1 = Addr.getOperand(0);
+    R2 = Addr.getOperand(1);
+    return true;
+  }
+
+  R1 = Select(Addr);
   R2 = CurDAG->getRegister(V8::G0, MVT::i32);
   return true;
 }
 
-bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand N, SDOperand &Base,
+bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
                                        SDOperand &Offset) {
-  // FIXME: This should obviously be smarter.
-  Base = Select(N);
+  if (Addr.getOpcode() == ISD::ADD) {
+    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
+      if (Predicate_simm13(CN)) {
+        Base = Addr.getOperand(0);
+        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
+        return true;
+      }
+  }
+  Base = Select(Addr);
   Offset = CurDAG->getTargetConstant(0, MVT::i32);
   return true;
 }
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 6f841cb0b7..6c1bf26005 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -90,10 +90,6 @@ def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
 // Section A.3 - Synthetic Instructions, p. 85
 // special cases of JMPL:
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
-  let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
-    def RET : F3_2<2, 0b111000,
-                   (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "ret $b, $c, $dst", []>;
   let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
     def RETL: F3_2<2, 0b111000, (ops),
                    "retl", [(ret)]>;