diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-07-19 06:37:02 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-07-19 06:37:02 +0000 |
| commit | 439661395fd2a2a832dba01c65bc88718528313c (patch) | |
| tree | e8091900c4d2f3278f5237358edeb7f22275cb77 /lib/Target/Sparc/SparcTargetMachine.cpp | |
| parent | 939ece1b5c6c2f142476b477daa573046fa1b8da (diff) | |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcTargetMachine.cpp')
| -rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.cpp | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index cbe6d8754e..218c4bc9bc 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -24,10 +24,10 @@ extern "C" void LLVMInitializeSparcTarget() { /// SparcTargetMachine ctor - Create an ILP32 architecture model /// -SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &CPU, - const std::string &FS, bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS), +SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + Reloc::Model RM, bool is64bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM), Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), @@ -51,15 +51,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, false) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - const std::string &TT, - const std::string &CPU, - const std::string &FS) - : SparcTargetMachine(T, TT, CPU, FS, true) { + StringRef TT, + StringRef CPU, + StringRef FS, Reloc::Model RM) + : SparcTargetMachine(T, TT, CPU, FS, RM, true) { } |