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authorChris Lattner <sabre@nondot.org>2009-09-15 17:46:24 +0000
committerChris Lattner <sabre@nondot.org>2009-09-15 17:46:24 +0000
commitdb486a6d5311944f61b92db9f6074944dbbdb242 (patch)
treec6ea58f21ac327940105e66d47fc76a3736459ad /lib/Target/Sparc/SparcISelDAGToDAG.cpp
parent307a7c48f15b087663b60d600d23afffb9e211e6 (diff)
several major improvements to the sparc backend: support for weak linkage
and PIC codegen. Patch by Venkatraman Govindaraju! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81877 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcISelDAGToDAG.cpp')
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp23
1 files changed, 19 insertions, 4 deletions
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index e1b9b59b40..071590f4d7 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -34,10 +34,13 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
/// make the right decision when generating code for different targets.
const SparcSubtarget &Subtarget;
+ SparcTargetMachine& TM;
+ MachineBasicBlock *CurBB;
public:
- explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
- : SelectionDAGISel(TM),
- Subtarget(TM.getSubtarget<SparcSubtarget>()) {
+ explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
+ : SelectionDAGISel(tm),
+ Subtarget(tm.getSubtarget<SparcSubtarget>()),
+ TM(tm) {
}
SDNode *Select(SDValue Op);
@@ -63,6 +66,9 @@ public:
// Include the pieces autogenerated from the target description.
#include "SparcGenDAGISel.inc"
+
+private:
+ SDNode* getGlobalBaseReg();
};
} // end anonymous namespace
@@ -70,12 +76,18 @@ public:
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SparcDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
-
+ CurBB = BB;
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
+SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
+ MachineFunction *MF = CurBB->getParent();
+ unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
+ return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
+}
+
bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
@@ -149,6 +161,9 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
switch (N->getOpcode()) {
default: break;
+ case SPISD::GLOBAL_BASE_REG:
+ return getGlobalBaseReg();
+
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.