diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:14:17 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:14:17 +0000 |
| commit | abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0 (patch) | |
| tree | e069f4a1e4f097051a048d5653efb601c89030c1 /lib/Target/R600/R600Schedule.td | |
| parent | e332e3559b5c09040de1528920006756e0962d6a (diff) | |
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600Schedule.td')
| -rw-r--r-- | lib/Target/R600/R600Schedule.td | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/lib/Target/R600/R600Schedule.td b/lib/Target/R600/R600Schedule.td index 7ede181c51..78a460ae9d 100644 --- a/lib/Target/R600/R600Schedule.td +++ b/lib/Target/R600/R600Schedule.td @@ -24,7 +24,7 @@ def AnyALU : InstrItinClass; def VecALU : InstrItinClass; def TransALU : InstrItinClass; -def R600_EG_Itin : ProcessorItineraries < +def R600_VLIW5_Itin : ProcessorItineraries < [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], [], [ @@ -34,3 +34,14 @@ def R600_EG_Itin : ProcessorItineraries < InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> ] >; + +def R600_VLIW4_Itin : ProcessorItineraries < + [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL], + [], + [ + InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, + InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>, + InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>, + InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> + ] +>; |