diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
| commit | a7a5854f1c3710f4bedf069be4771b81e449f2a3 (patch) | |
| tree | 438c2801d45b3995eed10e57be580d2d2797f172 /lib/Target/PowerPC/PPCSubtarget.cpp | |
| parent | 6557f186896b9a4f57ea354ee04e0c74c389e0e1 (diff) | |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCSubtarget.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index 607771b2ca..b228ba7a9c 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -73,8 +73,8 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit) : StackAlignment(16) , InstrItins() , IsGigaProcessor(false) - , Is64Bit(false) - , Has64BitRegs(false) + , Has64BitSupport(false) + , Use64BitRegs(false) , HasAltivec(false) , HasFSQRT(false) , HasSTFIWX(false) |