diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-18 23:24:50 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-18 23:24:50 +0000 |
| commit | 3f852b45fcfb0dde647eff77f9186378c3f0448a (patch) | |
| tree | f30130efcea0d5f3892636132b7dcf9ce57d95b3 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 329cdc3801506fc8b241005f7d1401cca84861ee (diff) | |
MFLR doesn't take an operand, the LR register is implicit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index ce6c46c888..8d76ba363d 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -83,7 +83,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, }; unsigned OC = Opcode[getIdx(getClass(SrcReg))]; if (SrcReg == PPC::LR) { - BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR); + BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); } else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) { BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); |