diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-07 05:00:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-07 05:00:52 +0000 |
| commit | eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2 (patch) | |
| tree | b97b985fda4d63fbdc41248a4de5c9462fea7478 /lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 602b02a8f47dfe3c396f50de3afd6a458c5e88b0 (diff) | |
Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index dc84075eba..2af1099355 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -57,7 +57,8 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2 + } else if (oc == PPC::FMRS || oc == PPC::FMRD || + oc == PPC::FMRSD) { // fmr r1, r2 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && |