diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-01 01:35:02 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-01 01:35:02 +0000 |
| commit | 919c032fa4511468aadc6f50d6ed9c50890710b3 (patch) | |
| tree | c6e36c019079fd98cd9e480de3f83c223eb8ea2f /lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | f85a55b09657094a1e3954728c7f4ca5bdb6f56a (diff) | |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 3ec78e3456..dc84075eba 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -57,7 +57,7 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC::FMR) { // fmr r1, r2 + } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && |