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| author | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-22 17:54:37 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-22 17:54:37 +0000 |
| commit | 7847fcac174bdda94373447676526af1bb1bc630 (patch) | |
| tree | 7492c15679992281d26f513e32d707ab86618bcf /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | dadc96f07a66dc8b381d16c5906a42a6ecdca213 (diff) | |
Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21452 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 84c05cb637..a516a8b3c8 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -263,8 +263,9 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { std::pair<SDOperand, SDOperand> PPC32TargetLowering::LowerCallTo(SDOperand Chain, - const Type *RetTy, bool isVarArg, - SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { + const Type *RetTy, bool isVarArg, + SDOperand Callee, ArgListTy &Args, + SelectionDAG &DAG) { // args_to_use will accumulate outgoing args for the ISD::CALL case in // SelectExpr to use to put the arguments in the appropriate registers. std::vector<SDOperand> args_to_use; @@ -2366,7 +2367,7 @@ void ISel::Select(SDOperand N) { case 3: assert(N.getOperand(1).getValueType() == MVT::i32 && N.getOperand(2).getValueType() == MVT::i32 && - "Unknown two-register value!"); + "Unknown two-register value!"); Select(N.getOperand(0)); Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(2)); |
