diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-31 17:48:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-31 17:48:04 +0000 |
| commit | 5dd7fea3f2fdcca7f2ab092d0042b9b0151449fd (patch) | |
| tree | 686da38291a5f52bca4200aaff3b69e1e64b149b /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 7383ce4127f0e1d9ff4eaaa7dac8e71e02d860c6 (diff) | |
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23170 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 50b10e41f1..b1c4a8b324 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -781,6 +781,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Reg = Result = (N.getValueType() != MVT::Other) ? MakeReg(N.getValueType()) : 1; break; + case ISD::AssertSext: + case ISD::AssertZext: + // Don't allocate a vreg for these nodes. + return Reg = SelectExpr(N.getOperand(0)); case ISD::TAILCALL: case ISD::CALL: // If this is a call instruction, make sure to prepare ALL of the result |