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| author | Chris Lattner <sabre@nondot.org> | 2005-08-18 23:24:50 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-18 23:24:50 +0000 |
| commit | 3f852b45fcfb0dde647eff77f9186378c3f0448a (patch) | |
| tree | f30130efcea0d5f3892636132b7dcf9ce57d95b3 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 329cdc3801506fc8b241005f7d1401cca84861ee (diff) | |
MFLR doesn't take an operand, the LR register is implicit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 5052c5deca..3ca7cd6c61 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -437,7 +437,7 @@ unsigned ISel::getGlobalBaseReg() { MachineBasicBlock::iterator MBBI = FirstMBB.begin(); GlobalBaseReg = MakeIntReg(); BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); - BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR); + BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg); GlobalBaseInitialized = true; } return GlobalBaseReg; |