diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-30 00:45:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-30 00:45:18 +0000 |
| commit | 6de08f4377302cb73ca6a378410889be423af20f (patch) | |
| tree | dc205c257ed6ede20da192de3ad45b2ef34f4e2c /lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 8f838720ad578349e7929b32fa9117aa317bb3a5 (diff) | |
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23140 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 57bf66e9ef..dad4c9fd2e 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -111,6 +111,10 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && MVT::isFloatingPoint(Op.getOperand(2).getValueType())) { ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); + + // Cannot handle SETEQ/SETNE. + if (CC == ISD::SETEQ || CC == ISD::SETNE) break; + MVT::ValueType ResVT = Op.getValueType(); MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); |