diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-26 20:25:03 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-26 20:25:03 +0000 |
| commit | 0bbea954331b8f08afa5b094dfb0841829c70eaa (patch) | |
| tree | 366b80f259411786aef2c8a6c4d28c1c67fad3ee /lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 9fdd6e3f50b7fdafff9aa0e1bac0bd2a78d03d71 (diff) | |
Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 7d46477b33..d84552c5c0 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -125,34 +125,34 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETUGE: case ISD::SETGE: - return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV); + return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); case ISD::SETUGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETULE: case ISD::SETLE: - return DAG.getTargetNode(PPC::FSEL, ResVT, - DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV); } switch (CC) { default: assert(0 && "Invalid FSEL condition"); abort(); case ISD::SETULT: case ISD::SETLT: - return DAG.getTargetNode(PPC::FSEL, ResVT, - DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV,TV); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV); case ISD::SETUGE: case ISD::SETGE: - return DAG.getTargetNode(PPC::FSEL, ResVT, - DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV,FV); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV); case ISD::SETUGT: case ISD::SETGT: - return DAG.getTargetNode(PPC::FSEL, ResVT, - DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV,TV); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV); case ISD::SETULE: case ISD::SETLE: - return DAG.getTargetNode(PPC::FSEL, ResVT, - DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV,FV); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV); } } break; |