Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.

8-byte align doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 14 deletions

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index a468c5eb75..9a9752c73b 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -60,6 +60,21 @@ namespace {
       return static_cast<PowerPCTargetMachine&>(TM);
     }
 
+    unsigned enumRegToMachineReg(unsigned enumReg) {
+      switch (enumReg) {
+      default: assert(0 && "Unhandled register!"); break;
+      case PPC::CR0:  return  0;
+      case PPC::CR1:  return  1;
+      case PPC::CR2:  return  2;
+      case PPC::CR3:  return  3;
+      case PPC::CR4:  return  4;
+      case PPC::CR5:  return  5;
+      case PPC::CR6:  return  6;
+      case PPC::CR7:  return  7;
+      }
+      abort();
+    }
+
     /// printInstruction - This method is automatically generated by tablegen
     /// from the instruction set description.  This method returns true if the
     /// machine instruction was sufficiently described to print it, otherwise it
@@ -141,22 +156,16 @@ namespace {
                        MVT::ValueType VT) {
       unsigned char value = MI->getOperand(OpNo).getImmedValue();
       assert(value <= 3 && "Invalid crbit argument!");
-      unsigned RegNo, CCReg = MI->getOperand(OpNo-1).getReg();
-      switch (CCReg) {
-      case PPC::CR0:  RegNo = 0; break;
-      case PPC::CR1:  RegNo = 1; break;
-      case PPC::CR2:  RegNo = 2; break;
-      case PPC::CR3:  RegNo = 3; break;
-      case PPC::CR4:  RegNo = 4; break;
-      case PPC::CR5:  RegNo = 5; break;
-      case PPC::CR6:  RegNo = 6; break;
-      case PPC::CR7:  RegNo = 7; break;
-      default:
-        std::cerr << "Unhandled reg in enumRegToRealReg!\n";
-        abort();
-      }
+      unsigned CCReg = MI->getOperand(OpNo-1).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
       O << 4 * RegNo + value;
     }
+    void printcrbitm(const MachineInstr *MI, unsigned OpNo,
+                       MVT::ValueType VT) {
+      unsigned CCReg = MI->getOperand(OpNo).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
+      O << (0x80 >> RegNo);
+    }
 
     virtual void printConstantPool(MachineConstantPool *MCP) = 0;
     virtual bool runOnMachineFunction(MachineFunction &F) = 0;