Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows

us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register.  This also requires some asm printer work
to satisfy the darwin assembler.

For
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

We now produce:
_foo:
        lvx v0, 0, r3
        vaddfp v0, v0, v0
        stvx v0, 0, r3
        blr

Instead of:
_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24872 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 1 deletions

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 9cf686353a..717b831086 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -189,7 +189,14 @@ namespace {
       O << ')';
     }
     void printMemRegReg(const MachineInstr *MI, unsigned OpNo) {
-      printOperand(MI, OpNo);
+      // When used as the base register, r0 reads constant zero rather than
+      // the value contained in the register.  For this reason, the darwin
+      // assembler requires that we print r0 as 0 (no r) when used as the base.
+      const MachineOperand &MO = MI->getOperand(OpNo);
+      if (MO.getReg() == PPC::R0)
+        O << '0';
+      else
+        O << TM.getRegisterInfo()->get(MO.getReg()).Name;
       O << ", ";
       printOperand(MI, OpNo+1);
     }