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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-19 16:28:30 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-19 16:28:30 +0000 |
| commit | 85aa4d0cc5ed00b875a8c9814ad25cc39199fbc5 (patch) | |
| tree | 4a5f0015d59fc1d068888f60dc444fa7754d3da1 /lib/Target/PowerPC/PPC64RegisterInfo.cpp | |
| parent | 1e67d4d7bae24793de849a5a97f7e194fd2f741a (diff) | |
Wrap long lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC64RegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPC64RegisterInfo.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/lib/Target/PowerPC/PPC64RegisterInfo.cpp index e30613041d..b394568acd 100644 --- a/lib/Target/PowerPC/PPC64RegisterInfo.cpp +++ b/lib/Target/PowerPC/PPC64RegisterInfo.cpp @@ -72,11 +72,10 @@ void PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, int FrameIdx) const { - const TargetRegisterClass *RC = getRegClass(SrcReg); static const unsigned Opcode[] = { PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD }; - + const TargetRegisterClass *RC = getRegClass(SrcReg); unsigned OC = Opcode[getIdx(RC)]; if (SrcReg == PPC::LR) { BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11); @@ -204,13 +203,15 @@ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { // convert into indexed form of the instruction // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 - unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()]; + unsigned NewOpcode = + const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()]; assert(NewOpcode && "No indexed form of load or store available!"); MI.setOpcode(NewOpcode); MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); MI.SetMachineOperandReg(2, PPC::R0); } else { - MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset); + MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, + Offset); } } |