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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-27 20:10:01 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-27 20:10:01 +0000 |
| commit | 2d86ea21dd76647cb054fd5d27df9e49efc672b6 (patch) | |
| tree | 87a965525520ccbd1d200407f54627b3697cdb6a /lib/Target/PowerPC/PPC64ISelPattern.cpp | |
| parent | 22cab6c752c75f81c05c679befd437e613138f6f (diff) | |
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21599 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC64ISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPC64ISelPattern.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp index e5c2f40e3c..1e72bf0ba6 100644 --- a/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -176,7 +176,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN, DAG.getConstant(SubregOffset, MVT::i64)); - argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN); + argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); } // Every 4 bytes of argument space consumes one of the GPRs available for @@ -204,7 +204,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]); SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot()); SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), - Val, FIN); + Val, FIN, DAG.getSrcValue(NULL)); MemOps.push_back(Store); // Increment the address by eight for the next argument to store SDOperand PtrOff = DAG.getConstant(8, getPointerTy()); @@ -285,7 +285,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, --GPR_remaining; } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff)); + Args[i].first, PtrOff, DAG.getSrcValue(NULL))); } ArgOffset += 8; break; @@ -296,11 +296,11 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, --FPR_remaining; if (isVarArg) { SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff); + Args[i].first, PtrOff, DAG.getSrcValue(NULL)); MemOps.push_back(Store); // Float varargs are always shadowed in available integer registers if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff); + SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, DAG.getSrcValue(NULL)); MemOps.push_back(Load); args_to_use.push_back(Load); --GPR_remaining; @@ -315,7 +315,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, } } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff)); + Args[i].first, PtrOff, DAG.getSrcValue(NULL))); } ArgOffset += 8; break; @@ -351,7 +351,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, MVT::ValueType ArgVT = getValueType(ArgTy); SDOperand Result; if (!isVANext) { - Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList); + Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL)); } else { Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, DAG.getConstant(8, VAList.getValueType())); |