Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 11 insertions, 7 deletions

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 2d016c67d4..4a919a0a28 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -118,7 +118,7 @@ insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
   BuildMI(MBB, MI, get(Mips::NOP));
 }
 
-void MipsInstrInfo::
+bool MipsInstrInfo::
 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
              unsigned DestReg, unsigned SrcReg,
              const TargetRegisterClass *DestRC,
@@ -141,10 +141,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
       BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
     else if ((SrcRC == Mips::CCRRegisterClass) && 
              (SrcReg == Mips::FCR31))
-      return; // This register is used implicitly, no copy needed.
+      return true; // This register is used implicitly, no copy needed.
     else if ((DestRC == Mips::CCRRegisterClass) && 
              (DestReg == Mips::FCR31))
-      return; // This register is used implicitly, no copy needed.
+      return true; // This register is used implicitly, no copy needed.
     else if ((DestRC == Mips::HILORegisterClass) &&
              (SrcRC == Mips::CPURegsRegisterClass)) {
       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
@@ -154,9 +154,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
       BuildMI(MBB, I, get(Opc), DestReg);
     } else
-      assert (0 && "DestRC != SrcRC, Can't copy this register");
+      // DestRC != SrcRC, Can't copy this register
+      return false;
 
-    return;
+    return true;
   }
 
   if (DestRC == Mips::CPURegsRegisterClass)
@@ -169,7 +170,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   else if (DestRC == Mips::AFGR64RegisterClass)
     BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
   else
-    assert (0 && "Can't copy this register");
+    // Can't copy this register
+    return false;
+  
+  return true;
 }
 
 void MipsInstrInfo::
diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h
index fc7c326d85..7615c71555 100644
--- a/lib/Target/Mips/MipsInstrInfo.h
+++ b/lib/Target/Mips/MipsInstrInfo.h
@@ -169,7 +169,7 @@ public:
   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond) const;
-  virtual void copyRegToReg(MachineBasicBlock &MBB, 
+  virtual bool copyRegToReg(MachineBasicBlock &MBB, 
                             MachineBasicBlock::iterator I,
                             unsigned DestReg, unsigned SrcReg,
                             const TargetRegisterClass *DestRC,