diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-12 22:14:24 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-12 22:14:24 +0000 |
| commit | 9367b8d4f254d9e5cccb15334cc1a969c5be0d31 (patch) | |
| tree | 74feb8a547863aa51787003647cfbb41275f4afe /lib/Target/Mips/MipsSEISelLowering.cpp | |
| parent | 0fda0f397621a6b50812622a73f0991768662491 (diff) | |
[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSEISelLowering.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 805228b6bc..70ba985f3e 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -45,12 +45,17 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) setOperationAction(Opc, VecTys[i], Expand); + setOperationAction(ISD::ADD, VecTys[i], Legal); + setOperationAction(ISD::SUB, VecTys[i], Legal); setOperationAction(ISD::LOAD, VecTys[i], Legal); setOperationAction(ISD::STORE, VecTys[i], Legal); setOperationAction(ISD::BITCAST, VecTys[i], Legal); } } + if (Subtarget->hasDSPR2()) + setOperationAction(ISD::MUL, MVT::v2i16, Legal); + if (!TM.Options.UseSoftFloat) { addRegisterClass(MVT::f32, &Mips::FGR32RegClass); |