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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-09 04:45:36 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-09 04:45:36 +0000 |
| commit | 7b76da145be2b3b7518ca42b43a903eabd52e1b7 (patch) | |
| tree | 15c41b5f8967962bf4f76caca28d7708a6c24c0b /lib/Target/Mips/MipsInstrInfo.cpp | |
| parent | b4d1bc989eec1e9369a6a575b6d9190467babb5e (diff) | |
Fixe typos and 80 column size problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 403adece96..687237f972 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -289,7 +289,8 @@ foldMemoryOperand(MachineFunction &MF, case Mips::FMOV_D32: if ((MI->getOperand(0).isRegister()) && (MI->getOperand(1).isRegister())) { - const TargetRegisterClass *RC = RI.getRegClass(MI->getOperand(0).getReg()); + const TargetRegisterClass + *RC = RI.getRegClass(MI->getOperand(0).getReg()); unsigned StoreOpc, LoadOpc; if (RC == Mips::FGR32RegisterClass) { |