CellSPU:

- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
  to the constant pool when they correspond to SPU's shufb instruction's
  special mask values. This avoids the overhead of performing a shuffle on a
  zero-filled vector just to get the special constant when the memory load
  suffices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 4 deletions

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 8623f30112..135164f3d9 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -60,9 +60,6 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
                           unsigned& SrcSR, unsigned& DstSR) const {
   SrcSR = DstSR = 0;  // No sub-registers.
 
-  // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
-  // cases where we can safely say that what's being done is really a move
-  // (see how PowerPC does this -- it's the model for this code too.)
   switch (MI.getOpcode()) {
   default:
     break;
@@ -167,7 +164,7 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
            MI.getOperand(1).isReg() &&
            "invalid SPU OR<type>_<vec> or LR instruction!");
     if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
-      sourceReg = MI.getOperand(0).getReg();
+      sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
       return true;
     }