diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 21:54:09 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 21:54:09 +0000 |
| commit | 3e98fde96bfeb346fb32bc1be3d667da66436592 (patch) | |
| tree | 91c554cb17db92ee64d8ff3879365646c2076e3c /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 9b5cb04a0a784ff35de93d07341b6616a15110d0 (diff) | |
initial fp support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19847 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 9bb9accb42..1a730b31e7 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -26,7 +26,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == Alpha::BIS) { // or r1, r2, r2 + if (oc == Alpha::BIS || oc == Alpha::CPYS) { // or r1, r2, r2 // cpys r1 r2 r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && |