diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-06 20:59:59 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-06 20:59:59 +0000 |
| commit | f77f395043218284b38717c9d6e58e3d7e2d6e76 (patch) | |
| tree | dfe954fd422f7a6d1c73b2fdbb6b13b9b16da04f /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 6d027f2e6fb2d25603eeaccfca71d5d576367a6d (diff) | |
fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21121 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 40 |
1 files changed, 32 insertions, 8 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 7d3b7cf96c..d046ce6b4c 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1703,34 +1703,58 @@ unsigned ISel::SelectExpr(SDOperand N) { N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2) { - Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); - BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(1).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255) + BuildMI(BB, isAdd?Alpha::S4ADDQi:Alpha::S4SUBQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } else if(N.getOperand(0).getOpcode() == ISD::SHL && N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3) { - Tmp1 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); - BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(1).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255) + BuildMI(BB, isAdd?Alpha::S8ADDQi:Alpha::S8SUBQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(1)); + BuildMI(BB, isAdd?Alpha::S8ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } //Position prevents subs else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd & N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2) { - Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); - BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(0).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255) + BuildMI(BB, Alpha::S4ADDQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd && N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3) { - Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); - BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + if (N.getOperand(0).getOpcode() == ISD::Constant && + cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255) + BuildMI(BB, Alpha::S8ADDQi, 2, Result).addReg(Tmp2) + .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue()); + else { + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); + } } //small addi else if(N.getOperand(1).getOpcode() == ISD::Constant && |