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authorAndrew Lenharth <andrewl@lenharth.org>2005-03-11 17:48:05 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-03-11 17:48:05 +0000
commite87f6c31d24158b6e16eb0bddafdcf9d453bebad (patch)
treef208750aabd65ad08bc374b41e2eacd0b454b6ec /lib/Target/Alpha/AlphaISelPattern.cpp
parentd03b3bc0088abb0206f77cdbf2c2cc3a623d9591 (diff)
remove a pseudo instruction and improve inline constant generation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20563 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp32
1 files changed, 29 insertions, 3 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 7eaa3e4fc0..ffe825971e 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -326,6 +326,25 @@ public:
};
}
+//These describe LDAx
+static const int64_t IMM_LOW = 0xffffffffffff8000LL;
+static const int IMM_HIGH = 0x0000000000007fffLL;
+static const int IMM_MULT = 65536;
+
+static long getUpper16(long l)
+{
+ long y = l / IMM_MULT;
+ if (l % IMM_MULT > IMM_HIGH)
+ ++y;
+ return y;
+}
+
+static long getLower16(long l)
+{
+ long h = getUpper16(l);
+ return l - h * IMM_MULT;
+}
+
static unsigned GetSymVersion(unsigned opcode)
{
switch (opcode) {
@@ -1447,9 +1466,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::Constant:
{
- unsigned long val = cast<ConstantSDNode>(N)->getValue();
- if (val < 32000 && (long)val > -32000)
- BuildMI(BB, Alpha::LOAD_IMM, 1, Result).addImm((long)val);
+ int64_t val = (long)cast<ConstantSDNode>(N)->getValue();
+ if (val <= IMM_HIGH && val >= IMM_LOW) {
+ BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
+ }
+ else if (val <= (int64_t)IMM_HIGH + (int64_t)IMM_HIGH * (int64_t)IMM_MULT &&
+ val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
+ Tmp1 = MakeReg(MVT::i64);
+ BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
+ BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
+ }
else {
MachineConstantPool *CP = BB->getParent()->getConstantPool();
ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);