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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-27 00:52:26 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-27 00:52:26 +0000 |
| commit | c0d502e20fcdfc4141e90ce965eec1f9a4365287 (patch) | |
| tree | 1fe754f433adfaf56c319e4b15337e4b6063484d /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 51d3ab4ad43697f2b92b0fe0a400f116dd7c51d0 (diff) | |
minor bug fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 3092a11a39..0e1cf14425 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -157,7 +157,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) case MVT::i32: case MVT::i64: BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]); - argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)))); + argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64))); argPreg.push_back(args_int[count - 1]); break; } |