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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-04 20:07:21 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-04 20:07:21 +0000 |
| commit | 619fb527646479ebb031ce1fe0803324c89740d3 (patch) | |
| tree | 04c21bd0b68035b27e110a76b70507eccea36278 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 2f5bca5c153b0372bb74b0eda111d8a084983dd9 (diff) | |
check the correct VT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22332 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index ed285a3d9f..bef529308e 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1642,7 +1642,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Select(Chain); unsigned r = dyn_cast<RegSDNode>(Node)->getReg(); //std::cerr << "CopyFromReg " << Result << " = " << r << "\n"; - if (isFP) + if (MVT::isFloatingPoint(N.getValue(0).getValueType())) BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r); else BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r); |