diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-07 14:18:13 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-07 14:18:13 +0000 |
| commit | 273a1f956f5bb58955515601d90279bf4c031fc6 (patch) | |
| tree | f4b4b890293d8d90806d9beda0ce9806a04f3cc5 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 706be918ca917ae38564f0b9940b77ffaf0ddbcf (diff) | |
It wasn't happy about this either
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21133 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 6c3a87a2ac..5df40ca154 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1755,7 +1755,7 @@ unsigned ISel::SelectExpr(SDOperand N) { BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1); } } - else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd && + else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd && N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3) { |