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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:02:55 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 23:02:55 +0000 |
| commit | 2729e614fa85347483d2f3ab209ebbc9a4e88bcd (patch) | |
| tree | 070e4f2521ac378f270e3222ff770de47cda6911 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 8b91c77385a055474d271aa8c10f0382fdeaafeb (diff) | |
generate chain result
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 3218f03d63..ec3479d15f 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -551,6 +551,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { case ISD::READCYCLECOUNTER: Select(N.getOperand(0)); //Select chain + if (Result != notIn) + ExprMap[N.getValue(1)] = notIn; // Generate the token + else + Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); + BuildMI(BB, Alpha::RPCC, 1, Result).addReg(Alpha::R31); return Result; |