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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-05-31 18:37:16 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-05-31 18:37:16 +0000 |
| commit | 14f30c927dd6ad12974df653c681d21524c532f1 (patch) | |
| tree | c80d97138ef129ac8aad2ec107bf86caa96717b8 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | fd5e4b778f6c1b3660f341b87374042780b4aca0 (diff) | |
switch to the new live in thing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22186 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 59c59981f8..deed1905d6 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -212,8 +212,8 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) case MVT::i64: args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT)); argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot()); - // if (VT != MVT::i64) - // argt = DAG.getNode(ISD::TRUNCATE, VT, argt); + if (VT != MVT::i64) + argt = DAG.getNode(ISD::TRUNCATE, VT, argt); break; } DAG.setRoot(argt.getValue(1)); |