diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 01:24:38 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 01:24:38 +0000 |
| commit | 0298118cbbe61c1850db0a09b4d289819c7cf187 (patch) | |
| tree | a17a348ce129ead5d52aab4a6ee0636454723902 /lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 3576c84baf5c1a5e0fb37b48c67bb893397011b1 (diff) | |
add some operations, fix others. should compile several more tests now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19843 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 7862aaf164..5fa16d0e69 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -50,6 +50,10 @@ namespace { setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand); setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand); + setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + + computeRegisterProperties(); // addLegalFPImmediate(+0.0); // FLD0 @@ -654,9 +658,20 @@ unsigned ISel::SelectExpr(SDOperand N) { } case ISD::UREM: + case ISD::SREM: + case ISD::SDIV: + case ISD::UDIV: + //FIXME: alpha really doesn't support any of these operations, + // the ops are expanded into special library calls with + // special calling conventions + switch(N.getOpcode()) { + case UREM: Opc = Alpha::REMQU; break; + case SREM: Opc = Alpha::REMQ; break; + case UDIV: Opc = Alpha::DIVQU; break; + case SDIV: Opc = Alpha::DIVQ; break; Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); - BuildMI(BB, Alpha::REMQU, 2, Result).addReg(Tmp1).addReg(Tmp2); + BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); return Result; case ISD::SELECT: |