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authorEvan Cheng <evan.cheng@apple.com>2008-09-02 06:51:36 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-09-02 06:51:36 +0000
commitacff339e391d23e748b69f61ae5c27fd5620c69f (patch)
tree74ccefbef7593e6745946f0ae617e9377d011e7f /lib/Target/Alpha/AlphaCodeEmitter.cpp
parented63214fcbebcaf989dbc6a5bf7c3b6df67732f5 (diff)
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaCodeEmitter.cpp')
-rw-r--r--lib/Target/Alpha/AlphaCodeEmitter.cpp14
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index 51a1404f32..40e14135a4 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -33,7 +33,8 @@ namespace {
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
///
- int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO);
public:
static char ID;
@@ -55,7 +56,7 @@ namespace {
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
- unsigned getBinaryCodeForInstr(MachineInstr &MI);
+ unsigned getBinaryCodeForInstr(const MachineInstr &MI);
private:
void emitBasicBlock(MachineBasicBlock &MBB);
@@ -87,7 +88,7 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
- MachineInstr &MI = *I;
+ const MachineInstr &MI = *I;
switch(MI.getOpcode()) {
default:
MCE.emitWordLE(getBinaryCodeForInstr(*I));
@@ -141,10 +142,11 @@ static unsigned getAlphaRegNumber(unsigned Reg) {
}
}
-int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) {
- int rv = 0; // Return value; defaults to 0 for unhandled cases
- // or things that get fixed up later by the JIT.
+ unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
+ // or things that get fixed up later by the JIT.
if (MO.isRegister()) {
rv = getAlphaRegNumber(MO.getReg());