Use TableGen to emit information for dwarf register numbers.

This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 23 insertions, 16 deletions

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index e97d6d2788..0d0f1d07ce 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -1657,5 +1657,10 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const {
   return 0;
 }
 
+int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+  assert(0 && "What is the dwarf register number");
+  return -1;
+}
+
 #include "ARMGenRegisterInfo.inc"
 
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index e0a2493d77..7d25fdcfc6 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -117,6 +117,8 @@ public:
   // Exception handling queries.
   unsigned getEHExceptionRegister() const;
   unsigned getEHHandlerRegister() const;
+
+  int getDwarfRegNum(unsigned RegNum) const;
 };
 
 } // end namespace llvm
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 3d2646e998..400c8c2649 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -25,22 +25,22 @@ class ARMFReg<bits<5> num, string n> : Register<n> {
 }
 
 // Integer registers
-def R0  : ARMReg< 0, "r0">,  DwarfRegNum<0>;
-def R1  : ARMReg< 1, "r1">,  DwarfRegNum<1>;
-def R2  : ARMReg< 2, "r2">,  DwarfRegNum<2>;
-def R3  : ARMReg< 3, "r3">,  DwarfRegNum<3>;
-def R4  : ARMReg< 4, "r4">,  DwarfRegNum<4>;
-def R5  : ARMReg< 5, "r5">,  DwarfRegNum<5>;
-def R6  : ARMReg< 6, "r6">,  DwarfRegNum<6>;
-def R7  : ARMReg< 7, "r7">,  DwarfRegNum<7>;
-def R8  : ARMReg< 8, "r8">,  DwarfRegNum<8>;
-def R9  : ARMReg< 9, "r9">,  DwarfRegNum<9>;
-def R10 : ARMReg<10, "r10">, DwarfRegNum<10>;
-def R11 : ARMReg<11, "r11">, DwarfRegNum<11>;
-def R12 : ARMReg<12, "r12">, DwarfRegNum<12>;
-def SP  : ARMReg<13, "sp">,  DwarfRegNum<13>;
-def LR  : ARMReg<14, "lr">,  DwarfRegNum<14>;
-def PC  : ARMReg<15, "pc">,  DwarfRegNum<15>;
+def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
+def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
+def R2  : ARMReg< 2, "r2">,  DwarfRegNum<[2]>;
+def R3  : ARMReg< 3, "r3">,  DwarfRegNum<[3]>;
+def R4  : ARMReg< 4, "r4">,  DwarfRegNum<[4]>;
+def R5  : ARMReg< 5, "r5">,  DwarfRegNum<[5]>;
+def R6  : ARMReg< 6, "r6">,  DwarfRegNum<[6]>;
+def R7  : ARMReg< 7, "r7">,  DwarfRegNum<[7]>;
+def R8  : ARMReg< 8, "r8">,  DwarfRegNum<[8]>;
+def R9  : ARMReg< 9, "r9">,  DwarfRegNum<[9]>;
+def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
+def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
+def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
+def SP  : ARMReg<13, "sp">,  DwarfRegNum<[13]>;
+def LR  : ARMReg<14, "lr">,  DwarfRegNum<[14]>;
+def PC  : ARMReg<15, "pc">,  DwarfRegNum<[15]>;
 
 // Float registers
 def S0  : ARMFReg< 0, "s0">;  def S1  : ARMFReg< 1, "s1">;