Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 42 insertions, 6 deletions

diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp
index a44ac07cd6..68a781c180 100644
--- a/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -236,7 +236,7 @@ static bool VerifyLowRegs(MachineInstr *MI) {
   unsigned Opc = MI->getOpcode();
   bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA     ||
                  Opc == ARM::t2LDMDB     || Opc == ARM::t2LDMIA_UPD ||
-                 Opc == ARM::t2LDMDB_UPD);
+                 Opc == ARM::t2LDMDB_UPD || Opc == ARM::t2LDRi12);
   bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
   bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -270,10 +270,12 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
     return false;
 
   unsigned Scale = 1;
+  bool HasBaseReg = true;
   bool HasImmOffset = false;
   bool HasShift = false;
   bool HasOffReg = true;
   bool isLdStMul = false;
+  bool InsertImmOffset = true;
   unsigned Opc = Entry.NarrowOpc1;
   unsigned OpNum = 3; // First 'rest' of operands.
   uint8_t  ImmLimit = Entry.Imm1Limit;
@@ -290,17 +292,50 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
       HasOffReg = false;
     }
     Scale = 4;
-    HasImmOffset = true;
+    if (MI->getOperand(2).isImm())
+      HasImmOffset = true;
+    else {
+      if (Entry.WideOpc == ARM::t2LDRi12) {
+        Opc = ARM::tLDRpci;
+        OpNum = 2;
+      }
+      HasImmOffset = false;
+      InsertImmOffset = false;
+      HasBaseReg = false;
+      HasOffReg = false;
+    }
     break;
   }
   case ARM::t2LDRBi12:
   case ARM::t2STRBi12:
-    HasImmOffset = true;
+    if (MI->getOperand(2).isImm())
+      HasImmOffset = true;
+    else {
+      if (Entry.WideOpc == ARM::t2LDRBi12) {
+        Opc = ARM::tLDRpci;
+        OpNum = 2;
+      }
+      HasImmOffset = false;
+      InsertImmOffset = false;
+      HasBaseReg = false;
+      HasOffReg = false;
+    }
     break;
   case ARM::t2LDRHi12:
   case ARM::t2STRHi12:
     Scale = 2;
-    HasImmOffset = true;
+    if (MI->getOperand(2).isImm())
+      HasImmOffset = true;
+    else {
+      if (Entry.WideOpc == ARM::t2LDRHi12) {
+        Opc = ARM::tLDRpci;
+        OpNum = 2;
+      }
+      HasImmOffset = false;
+      InsertImmOffset = false;
+      HasBaseReg = false;
+      HasOffReg = false;
+    }
     break;
   case ARM::t2LDRs:
   case ARM::t2LDRBs:
@@ -388,8 +423,9 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
   DebugLoc dl = MI->getDebugLoc();
   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
   if (!isLdStMul) {
-    MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
-    if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
+    MIB.addOperand(MI->getOperand(0));
+    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
+    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
       // tLDRSB and tLDRSH do not have an immediate offset field. On the other
       // hand, it must have an offset register.
       // FIXME: Remove this special case.