diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
| commit | dd364419ee64cd5bb234af006ce0cb285e4a84ca (patch) | |
| tree | 39b3a87aca20346bf316390cb68c42812ce683ab /lib/Target/ARM/Thumb2SizeReduction.cpp | |
| parent | 94a935f072452d00207b1e8c1da75c31bb2a5f9b (diff) | |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2SizeReduction.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2SizeReduction.cpp | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index f18f491f49..796927cac5 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -114,6 +114,22 @@ namespace { { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 }, + + // At this point it is safe to translate acquire loads to normal loads. + // There is no risk of reordering loads. + { ARM::ATOMIC_t2LDRi12, + ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 }, + { ARM::ATOMIC_t2LDRs, + ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, + { ARM::ATOMIC_t2LDRBi12, + ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, + { ARM::ATOMIC_t2LDRBs, + ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 }, + { ARM::ATOMIC_t2LDRHi12, + ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 }, + { ARM::ATOMIC_t2LDRHs, + ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, + { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 }, { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, @@ -341,7 +357,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, switch (Entry.WideOpc) { default: llvm_unreachable("Unexpected Thumb2 load / store opcode!"); - case ARM::t2LDRi12: + case ARM::t2LDRi12: case ARM::ATOMIC_t2LDRi12: case ARM::t2STRi12: if (MI->getOperand(1).getReg() == ARM::SP) { Opc = Entry.NarrowOpc2; @@ -353,7 +369,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, HasImmOffset = true; HasOffReg = false; break; - case ARM::t2LDRBi12: + case ARM::t2LDRBi12: case ARM::ATOMIC_t2LDRBi12: case ARM::t2STRBi12: HasImmOffset = true; HasOffReg = false; @@ -364,9 +380,9 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, HasImmOffset = true; HasOffReg = false; break; - case ARM::t2LDRs: - case ARM::t2LDRBs: - case ARM::t2LDRHs: + case ARM::t2LDRs: case ARM::ATOMIC_t2LDRs: + case ARM::t2LDRBs: case ARM::ATOMIC_t2LDRBs: + case ARM::t2LDRHs: case ARM::ATOMIC_t2LDRHs: case ARM::t2LDRSBs: case ARM::t2LDRSHs: case ARM::t2STRs: |