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authorJim Grosbach <grosbach@apple.com>2011-11-30 01:09:44 +0000
committerJim Grosbach <grosbach@apple.com>2011-11-30 01:09:44 +0000
commit98b05a57b67d1968381563c8cccbbb6c6cb65e3d (patch)
tree1f6868b8a57f7b66aca8c50621f1479c52e2a18f /lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
parent3d925d24e8c54cde05228258c25cc21687cad922 (diff)
ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
-rw-r--r--lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 6c6c02146f..ed2594e2ae 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -1029,3 +1029,10 @@ void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
}
+
+void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
+ unsigned OpNum,
+ raw_ostream &O) {
+ O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
+}
+