diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-09 23:33:27 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 23:33:27 +0000 |
| commit | de317f40f7a9962372adea162a12ec35a628efa1 (patch) | |
| tree | d7af7a15c6aa8999826b6d4ea5f64c62dfc2c3a6 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | d40aa24ebf2e67ae0802d15e1ff20373c1e9dc2f (diff) | |
Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 4e7e582c61..59bed8ddce 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -683,8 +683,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, unsigned Rs = fieldFromInstruction32(Val, 8, 4); // Register-register - DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rs, Address, Decoder); + if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { |