diff options
| author | Jim Grosbach <grosbach@apple.com> | 2012-03-06 23:10:38 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-06 23:10:38 +0000 |
| commit | 4d0983a4d734280d481bb56472fe44ad0ddc447d (patch) | |
| tree | 93f9ff122857f24e3bf44511080c1616b06e8f52 /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | c511c2827d9cebd16bc63041b5812f1fc5d57e06 (diff) | |
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index fcb85449e6..fe93a4c612 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1101,11 +1101,6 @@ public: return VectorList.Count == 4; } - bool isVecListTwoQ() const { - if (!isDoubleSpacedVectorList()) return false; - return VectorList.Count == 2; - } - bool isVecListDPairSpaced() const { if (!isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] @@ -1139,7 +1134,7 @@ public: .contains(VectorList.RegNum)); } - bool isVecListTwoQAllLanes() const { + bool isVecListDPairSpacedAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 2; } @@ -3169,8 +3164,10 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { case AllLanes: // Two-register operands have been converted to the // composite register classes. - if (Count == 2 && Spacing == 1) { - const MCRegisterClass *RC = &ARMMCRegisterClasses[ARM::DPairRegClassID]; + if (Count == 2) { + const MCRegisterClass *RC = (Spacing == 1) ? + &ARMMCRegisterClasses[ARM::DPairRegClassID] : + &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); } Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, |