diff options
| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-15 18:31:01 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-15 18:31:01 +0000 |
| commit | 5193e4ebe216dd5a07ab9cc58d40de5aafaa990c (patch) | |
| tree | af0fd56a4789a5e950a4ffaf8f62ff0d0ea5ff3e /lib/Target/ARM/ARMTargetTransformInfo.cpp | |
| parent | bcbf3fddef46f1f6e2f2408064c4b75e4b6c90f5 (diff) | |
ARM cost model: Fix costs for some vector selects
I was too pessimistic in r177105. Vector selects that fit into a legal register
type lower just fine. I was mislead by the code fragment that I was using. The
stores/loads that I saw in those cases came from lowering the conditional off
an address.
Changing the code fragment to:
%T0_3 = type <8 x i18>
%T1_3 = type <8 x i1>
define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2,
%T1_3* %blend, %T0_3* %storeaddr) {
%v0 = load %T0_3* %loadaddr
%v1 = load %T0_3* %loadaddr2
==> FROM:
;%c = load %T1_3* %blend
==> TO:
%c = icmp slt %T0_3 %v0, %v1
==> USE:
%r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1
store %T0_3 %r, %T0_3* %storeaddr
ret void
}
revealed this mistake.
radar://13403975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMTargetTransformInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMTargetTransformInfo.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMTargetTransformInfo.cpp b/lib/Target/ARM/ARMTargetTransformInfo.cpp index 61b39e9a50..7a32ffb787 100644 --- a/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -351,11 +351,6 @@ unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) { // Lowering of some vector selects is currently far from perfect. static const TypeConversionCostTblEntry<MVT> NEONVectorSelectTbl[] = { - { ISD::SELECT, MVT::v4i1, MVT::v4i8, 2*4 + 2*1 }, - { ISD::SELECT, MVT::v8i1, MVT::v8i8, 2*8 + 1 }, - { ISD::SELECT, MVT::v16i1, MVT::v16i8, 2*16 + 1 }, - { ISD::SELECT, MVT::v4i1, MVT::v4i16, 2*4 + 1 }, - { ISD::SELECT, MVT::v8i1, MVT::v8i16, 2*8 + 1 }, { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 }, { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 }, { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 }, |