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| author | Andrew Trick <atrick@apple.com> | 2012-08-08 02:44:16 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-08-08 02:44:16 +0000 |
| commit | d43b5c97cff06d7840b974ca84fa0639d2567968 (patch) | |
| tree | eb9de873f2da7cc46629dc7c007658844382a9e8 /lib/Target/ARM/ARMSubtarget.h | |
| parent | 3c417554caedde3a333755916701c8380606342a (diff) | |
Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.h')
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index e06c7c770a..b394061300 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -155,6 +155,9 @@ protected: /// TargetTriple - What processor and OS we're targeting. Triple TargetTriple; + /// SchedModel - Processor specific instruction costs. + const MCSchedModel *SchedModel; + /// Selected instruction itineraries (one entry per itinerary class.) InstrItineraryData InstrItins; |