diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-09-26 06:25:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-26 06:25:56 +0000 |
| commit | 9efce638d307b2c71bd7f0258d47501661434c27 (patch) | |
| tree | ff8e23600c1a2e9ba48a6010a2ec8a84c84f785b /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 61001b8bd47adcf413dbb5b2a8c95cf22ec4bf7a (diff) | |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index eda31b0ca9..e6d99e590c 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -183,8 +183,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - if (RC == ARM::GPRRegisterClass) { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); if (AFI->isThumbFunction()) @@ -192,10 +198,10 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, else BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0); - } else if (RC == ARM::SPRRegisterClass) + } else if (DestRC == ARM::SPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0); - else if (RC == ARM::DPRRegisterClass) + else if (DestRC == ARM::DPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0); else |