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| author | Eric Christopher <echristo@gmail.com> | 2013-04-22 13:51:44 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2013-04-22 13:51:44 +0000 |
| commit | b929b13c77a316dd9efd278399b9577fafca9a84 (patch) | |
| tree | 8d05c22976a2b220064b7ba23dd9ad1f66a98c21 /lib/Target/ARM/ARMFastISel.cpp | |
| parent | f38bc31b0d37605e70f350d7862cfac5727efe49 (diff) | |
Remove variable store that is never read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180014 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index c5b9e50e0c..c678e8eaf0 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -2605,7 +2605,7 @@ unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned Opc; bool isBoolZext = false; - const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32); + const TargetRegisterClass *RC = 0; switch (SrcVT.SimpleTy) { default: return 0; case MVT::i16: |