Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 11 insertions, 3 deletions

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 3d065d83e6..fa06bf7eeb 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -822,11 +822,15 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
   unsigned Opc = MI->getOpcode();
   unsigned SrcReg, DstReg;
 
-  // Special case: tPUSH does not have src/dst regs.
-  if (Opc == ARM::tPUSH) {
+  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
+    // Two special cases:
+    // 1) tPUSH does not have src/dst regs.
+    // 2) for Thumb1 code we sometimes materialize the constant via constpool
+    // load. Yes, this is pretty fragile, but for now I don't see better
+    // way... :(
     SrcReg = DstReg = ARM::SP;
   } else {
-    SrcReg =  MI->getOperand(1).getReg();
+    SrcReg = MI->getOperand(1).getReg();
     DstReg = MI->getOperand(0).getReg();
   }
 
@@ -875,6 +879,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
         assert(0 && "Unsupported opcode for unwinding information");
       case ARM::MOVr:
       case ARM::tMOVgpr2gpr:
+      case ARM::tMOVgpr2tgpr:
         Offset = 0;
         break;
       case ARM::ADDri:
@@ -891,6 +896,9 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
       case ARM::tADDrSPi:
         Offset = -MI->getOperand(2).getImm()*4;
         break;
+      case ARM::tLDRpci:
+        assert(0 && "Not implemented yet!");
+        break;
       }
 
       if (DstReg == FramePtr && FramePtr != ARM::SP)