diff options
| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
| commit | dfe076af9879eb68a7b8331f9c02eecf563d85be (patch) | |
| tree | e1c1993543cc51da36b9cfc99ca0e7104a28ef33 /lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | 19254c49a8752fe8c6fa648a6eb29f20a1f62c8b (diff) | |
Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 017b50969d..38d0e8edde 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -77,10 +77,12 @@ static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, + unsigned RegNo, uint64_t Address, + const void *Decoder); static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, unsigned OptionHiS, @@ -143,11 +145,10 @@ static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, - llvm::MCInst &Inst, - unsigned Val, - uint64_t Address, - const void *Decoder); +static DecodeStatus +DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, + llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, unsigned Val, @@ -247,7 +248,8 @@ DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, } static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const void *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -460,8 +462,10 @@ static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, } // ASR and LSR have more specific patterns so they won't get here: - assert(!(ImmS == 31 && !SF && Opc != BFM) && "shift should have used auto decode"); - assert(!(ImmS == 63 && SF && Opc != BFM) && "shift should have used auto decode"); + assert(!(ImmS == 31 && !SF && Opc != BFM) + && "shift should have used auto decode"); + assert(!(ImmS == 63 && SF && Opc != BFM) + && "shift should have used auto decode"); // Extension instructions similarly: if (Opc == SBFM && ImmR == 0) { |