aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2010-05-12 23:59:42 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-12 23:59:42 +0000
commitde7dea2e44ea59674acb5680482cd516c6fce3bb (patch)
tree29f136973962d916a72d2333d35ea712c04ccab0 /lib/CodeGen
parent3519f9d7d179ac1a77a4721b2e5f8123f95af418 (diff)
Do not attempt copy coalescing if the source and dest sub-register indices do not match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103679 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/RegAllocLocal.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 0a14e29237..6372559824 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -846,7 +846,8 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
unsigned SrcCopyPhysReg = 0U;
bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
- SrcCopySubReg, DstCopySubReg);
+ SrcCopySubReg, DstCopySubReg) &&
+ SrcCopySubReg == DstCopySubReg;
if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
@@ -1154,7 +1155,8 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
// the register scavenger. See pr4100.)
if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
SrcCopySubReg, DstCopySubReg) &&
- SrcCopyReg == DstCopyReg && DeadDefs.empty())
+ SrcCopyReg == DstCopyReg && SrcCopySubReg == DstCopySubReg &&
+ DeadDefs.empty())
MBB.erase(MI);
}