diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-11-09 19:10:46 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-09 19:10:46 +0000 |
| commit | 8dc5cad8a255caa4d12d4eba20ad66f3959d161c (patch) | |
| tree | 380d7a4c7d4e4b08d5133644aa6e0c7add883845 /lib/CodeGen | |
| parent | 5ff839fbabe8b1d26cf4db5c541eb5d7942c25d6 (diff) | |
Don't attempt expensive pre-/post- indexed dag combine if target does not support them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31598 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8bbcd2651c..b74de8e843 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -190,9 +190,18 @@ namespace { bool isLoad = true; SDOperand Ptr; + MVT::ValueType VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { + VT = LD->getLoadedVT(); + if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && + !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) + return false; Ptr = LD->getBasePtr(); } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { + VT = ST->getStoredVT(); + if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && + !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) + return false; Ptr = ST->getBasePtr(); isLoad = false; } else @@ -281,8 +290,16 @@ namespace { SDOperand Ptr; MVT::ValueType VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { + VT = LD->getLoadedVT(); + if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && + !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) + return false; Ptr = LD->getBasePtr(); } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { + VT = ST->getStoredVT(); + if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && + !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) + return false; Ptr = ST->getBasePtr(); isLoad = false; } else @@ -299,7 +316,7 @@ namespace { SDOperand BasePtr; SDOperand Offset; ISD::MemIndexedMode AM = ISD::UNINDEXED; - if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) { + if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { if (Ptr == Offset) std::swap(BasePtr, Offset); if (Ptr != BasePtr) |