diff options
| author | Scott Michel <scottm@aero.org> | 2008-06-02 22:18:03 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2008-06-02 22:18:03 +0000 |
| commit | 8bf61e8c2a39bcf070c39848fea83eda57851ebb (patch) | |
| tree | a73a80f3763205767300ee4a008edd8cc8b17dbf /lib/CodeGen | |
| parent | 193c2358507b151ffbca2f0bb6fbfba55b60bdbd (diff) | |
Add necessary 64-bit support so that gcc frontend compiles (mostly). Current
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a6268e7340..3ec4181a2d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -4441,11 +4441,20 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); break; } - case ISD::SELECT: + case ISD::SELECT: { Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 + + unsigned VT2 = Tmp2.getValueType(); + assert(VT2 == Tmp3.getValueType() + && "PromoteOp: Operands 2 and 3 ValueTypes don't match"); + // Ensure tha NVT is the same as the operands' value types, because we + // cannot assume that TLI.getSetCCValueType() is constant. + if (NVT != VT2) + NVT = VT2; Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); break; + } case ISD::SELECT_CC: Tmp2 = PromoteOp(Node->getOperand(2)); // True Tmp3 = PromoteOp(Node->getOperand(3)); // False |