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authorChris Lattner <sabre@nondot.org>2006-03-22 00:12:37 +0000
committerChris Lattner <sabre@nondot.org>2006-03-22 00:12:37 +0000
commit3b9fa89fcaf3eb08397c4c68b60c72fc73f8ab44 (patch)
tree69e38093cd8501e24ea4ffa91ba8bbb11fde127e /lib/CodeGen
parent4a7da365460fb6c358729fbb5c86598ea90f1d86 (diff)
Enclose some variables in a scope to avoid error with some gcc versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26934 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 6c2b188b38..5a1aef7a7d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -859,7 +859,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
break;
- case ISD::VEXTRACT_VECTOR_ELT:
+ case ISD::VEXTRACT_VECTOR_ELT: {
// We know that operand #0 is the Vec vector. If the index is a constant
// or if the invec is a supported hardware type, we can use it. Otherwise,
// lower to a store then an indexed load.
@@ -897,10 +897,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
// It's now an extract from the appropriate high or low part.
Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
} else {
- // FIXME: IMPLEMENT STORE/LOAD lowering.
+ // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
assert(0 && "unimp!");
}
break;
+ }
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);